Crate itm_decode[−][src]
Expand description
A sans-I/O decoder for the ITM and DWT packet protocol as specifed in the ARMv7-M architecture reference manual, Appendix D4. Any references in this code base refers to this document.
Common abbreviations:
- ITM: instrumentation trace macrocell;
- PC: program counter;
- DWT: data watchpoint and trace unit;
- MSB: most significant bit;
- BE: big-endian;
Structs
ITM and DWT packet protocol decoder.
Enums
A header or payload byte failed to be decoded. The state of the decoder is now in an unknown state and manual intervention is required.
The decoder’s possible states. The default decoder state is Header
and will always return there after a maximum of two steps. (E.g. if
the current state is Syncing or HardwareSource, the next state
is Header again.)
Denotes the exception action taken by the processor. (Table D4-6)
Denotes the exception type (interrupt event) of the processor. (Table B1-4)
Denotes the type of memory access.
Indicates the relationship between the generation of the local timestamp packet and the corresponding ITM or DWT data packet. (Appendix D4.2.4)
The set of possible packet types that may be decoded.